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DDR3 SDRAM exposed: Inside a bleeding-edge, blazing-fast memory device
  For this second installment of we decided to really stretch our wings. We expect to normally devote this column to innovative blocks of analog circuitry from devices in the power-management, , RF, and consumer- markets—things that can be explained well in a Web environment. However, today we are going to go right down to an advanced 68-nm, 1-Gbit memory device, and talk a little about how it achieves the blazing speeds required in today's applications.

For at least two years now, DRAM manufacturers have been touting the advantages of DDR3 SDRAMs over the previous generation of DDR2 memories. These benefits include a lower operating voltage of 1.5V versus 1.8V, a power-consumption reduction of up to 30%, and the cost advantages inherent in using more advanced technologies. The primary benefit mentioned, of course, is the higher data-transfer rates. While DDR2's maximum transfer rate is just 800 Mbps, DDR3 is specified up to 1600 Mbps.

For the last couple of years DDR3 has held out a lot of promise, but the realization of that potential has been slow in coming. The first DDR3 chips on the market used older 90-nm technologies and were not available in the higher speed grades. Hence DDR2 SDRAMs have maintained their market dominance. But this is now changing as DDR3 chips are showing up in more advanced technologies and higher speed grades. A good example is the latest part from the world's No. 1 DRAM supplier, . Chipworks has just completed an analysis of this chip.

The K4B1G0846D-HCF8 is a 1-Gbit, high-speed CMOS, third-generation DDR3 SDRAM, internally configured as 16 Mbits × 8 I/Os × 8 banks. The K4B1G0846D-HCF8 uses an 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is designed to transfer two data words per clock cycle at the I/O pins. A single read or write access to the device consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. This version of the device achieves a data rate of 1066 Mbps on each I/O pin.

Samsung manufactures the K4B1G0846D-HCF8 in a four-metal, single-poly, 68-nm CMOS process, and mounts it in an 82-ball FBGA package。 This is the most advanced DDR3 process and design we have seen

release time :2008-11-4
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